Power saving techniques in computing devices

ABSTRACT

Aspects disclosed in the detailed description include power saving techniques in computing devices. In particular, as data is received by a modem processor in a computing device, the data is held until the expiration of a modem timer. The data is then passed to an application processor in the computing device over a peripheral component interconnect express (PCIe) interconnectivity bus. On receipt of the data from the modem processor, the application processor sends data held by the application processor to the modem processor over the PCIe interconnectivity bus. The application processor also has an uplink timer. If no data is received from the modem processor before expiration of the uplink timer, the application processor sends any collected data to the modem processor at expiration of the uplink timer. However, if data is received from the modem processor, the uplink timer is reset.

PRIORITY CLAIMS

The present application is a reissue continuation of U.S. patentapplication Ser. No. 17/240,496 filed on Apr. 26, 2021 and entitled“POWER SAVING TECHNIQUES IN COMPUTING DEVICES,” which is an applicationfor reissue of U.S. Pat. No. 9,535,490.

The present application '490 patent claims priority to U.S. ProvisionalPatent Application Ser. No. 61/916,498 filed on Dec. 16, 2013 andentitled “POWER SAVING TECHNIQUES IN COMPUTING DEVICES,” which isincorporated herein by reference in its entirety.

The present application '490 patent also claims priority to U.S.Provisional Patent Application Ser. No. 62/019,073 filed on Jun. 30,2014 and entitled “POWER SAVING TECHNIQUES IN COMPUTING DEVICES,” whichis incorporated herein by reference in its entirety.

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to power savingtechniques in computing devices.

II. Background

Computing devices are common within modem society. Ranging from small,mobile computing devices, such as a smart phone or tablet, to largeserver farms with numerous blades and memory banks, these devices areexpected to communicate across myriad networks while providing variousother base functions. While desktop devices and servers are generallyimmune to concerns about power consumption, mobile devices constantlystruggle to find a proper balance between available functions andbattery life. That is, as more functions are provided, power consumptionincreases, and battery life is shortened. Servers may likewise havepower consumption concerns when assembled in large server farms.

Concurrent with power consumption concerns, improvements in networkcommunications have increased data rates. For example, copper wires havebeen replaced with higher bandwidth fiber optic cables, and cellularnetworks have evolved from early Advanced Mobile Phone System (AMPS) andGlobal System for Mobile Communications (GSM) protocols to 4G and LongTerm Evolution (LTE) protocols capable of supporting much higher datarates. As the data rates have increased, the need to be able to processthese increased data rates within computing devices has also increased.Thus, earlier mobile computing devices may have had internal busesformed according to a High Speed Inter-Chip (HSIC) standard, universalserial bus (USB) standard (and particularly USB 2.0), or universalasynchronous receiver/transmitter (UART) standard. However, these busesdo not support current data rates.

In response to the need for faster internal buses, the peripheralcomponent interconnect express (PCIe) standard, as well as, latergenerations of USB (e.g., USB 3.0 and subsequent versions) have beenadopted for some mobile computing devices. However, while PCIe and USB3.0 can handle the high data rates currently being used, usage of suchbuses results in excessive power consumption and negatively impactsbattery life by shortening the time between recharging events.

SUMMARY OF THE DISCLOSURE

Aspects disclosed in the detailed description include power savingtechniques in computing devices. In particular, as data is received by amodem processor in a computing device, the data is held until theexpiration of a modem timer. The data is then passed to an applicationprocessor in the computing device over a peripheral componentinterconnect express (PCIe) interconnectivity bus. On receipt of thedata from the modem processor, the application processor sends data heldby the application processor to the modem processor over the PCIeinterconnectivity bus. The application processor also has an uplinktimer. If no data is received from the modem processor before expirationof the uplink timer, the application processor sends any collected datato the modem processor at expiration of the uplink timer. However, ifdata is received from the modem processor, the uplink timer is reset. Byholding or accumulating the data at a source processor in this fashion,unnecessary transitions between low power states and active states onthe PCIe bus are reduced and power is conserved.

In an alternate aspect, instead of initiating data transfer based on theexpiration of the downlink timer (with or without expiration of theuplink timer), accumulated data transfer may be initiated based onexpiration of just an uplink accumulation timer. The uplink accumulationtimer may be within a host or a device associated with theinterconnectivity bus.

In another alternate aspect, initiation of the data transfer may bebased on reaching a predefined threshold for a byte accumulation limitcounter. The byte accumulation limit counter is not mutually exclusiverelative to the other counters and may operate as an override mechanismfor one of the other accumulation timers. Use of such an override may beuseful in situations where a sudden burst of data arrives that wouldexceed buffer space and/or bus bandwidth. Likewise, instead of a bytecounter, a packet size counter or a “total number of packets” countermay be used to cover situations where numerous packets or a particularlylarge packet is delivered by the network.

In further aspects of the present disclosure, the timers may beoverridden by other factors or parameters. Such an override is alludedto above with the byte accumulation limit counters and the total numberof packets counter, which causes data transfers independently of thetimers. Other parameters may also override the timers, such as thepresence of low latency traffic (e.g., control messages), synchronizingthe uplink and downlink data transfers, or low latency quality ofservice requirements. When such traffic is present, an interrupt orother command may be used to initiate data transfers before expirationof a timer. Still other factors may override the timers, such as anindication that a device or host is not in an automatic polling mode.

In this regard in one aspect, a mobile terminal is disclosed. The mobileterminal comprises a modem timer. The mobile terminal also comprises amodem processor. The modem processor is configured to hold modemprocessor to application processor data until expiration of the modemtimer. The mobile terminal also comprises an application processor. Themobile terminal also comprises an interconnectivity bus communicativelycoupling the application processor to the modem processor. Theapplication processor is configured to hold application processor tomodem processor data until receipt of the modem processor to applicationprocessor data from the modem processor through the interconnectivitybus after which the application processor to modem processor data issent to the modem processor through the interconnectivity bus.

In another aspect, a method of controlling power consumption in acomputing device is disclosed. The method comprises holding datareceived by a modem processor from a remote network until expiration ofa downlink timer. The method also comprises passing the data received bythe modem processor to an application processor over aninterconnectivity bus. The method also comprises holding applicationdata generated by an application associated with the applicationprocessor for until receipt of the data from the modem processor orexpiration of an uplink timer, whichever occurs first.

In another aspect, a mobile terminal is disclosed. The mobile terminalcomprises a modem processor. The mobile terminal also comprises anapplication timer. The mobile terminal also comprises an applicationprocessor. The application processor is configured to hold applicationprocessor to modem processor data until expiration of the applicationtimer. The mobile terminal also comprises an interconnectivity buscommunicatively coupling the application processor to the modemprocessor. The modem processor is configured to hold modem processor toapplication processor data until receipt of the application processor tomodem processor data from the application processor through theinterconnectivity bus after which the modem processor to applicationprocessor data is sent to the application processor through theinterconnectivity bus.

In another aspect, a mobile terminal is disclosed. The mobile terminalcomprises a modem byte accumulation limit counter. The mobile terminalalso comprises a modem processor. The modem processor is configured tohold modem processor to application processor data until a predefinedthreshold of bytes has been reached by the modem byte accumulation limitcounter. The mobile terminal also comprises an application processor.The mobile terminal also comprises an interconnectivity buscommunicatively coupling the application processor to the modemprocessor. The application processor is configured to hold applicationprocessor to modem processor data until receipt of the modem processorto application processor data from the modem processor through theinterconnectivity bus after which the application processor to modemprocessor data is sent to the modem processor through theinterconnectivity bus.

With regards to another aspect, a mobile terminal is disclosed. Themobile terminal comprises a modem packet counter. The mobile terminalalso comprises a modem processor. The modem processor is configured tohold modem processor to application processor data until a predefinedthreshold of packets has been reached by the modem packet counter. Themobile terminal also comprises an application processor. The mobileterminal also comprises an interconnectivity bus communicativelycoupling the application processor to the modem processor. Theapplication processor is configured to hold application processor tomodem processor data until receipt of the modem processor to applicationprocessor data from the modem processor through the interconnectivitybus after which the application processor to modem processor data issent to the modem processor through the interconnectivity bus.

In another aspect, a mobile terminal is disclosed. The mobile terminalcomprises a modem processor. The mobile terminal also comprises anapplication byte counter. The mobile terminal also comprises anapplication processor. The application processor is configured to holdapplication processor to modem processor data until a predefinedthreshold of bytes has been reached by the application byte counter. Themobile terminal also comprises an interconnectivity bus communicativelycoupling the application processor to the modem processor. The modemprocessor is configured to hold modem processor to application processordata until receipt of the application processor to modem processor datafrom the application processor through the interconnectivity bus afterwhich the modem processor to application processor data is sent to theapplication processor through the interconnectivity bus.

In another aspect, a mobile terminal is disclosed. The mobile terminalcomprises a modem processor and an application packet counter. Themobile terminal also comprises an application processor. The applicationprocessor is configured to hold application processor to modem processordata until a predefined threshold of packets has been reached by theapplication packet counter. The mobile terminal comprises aninterconnectivity bus communicatively coupling the application processorto the modem processor. The modem processor is configured to hold themodem processor to application processor data until receipt of theapplication processor to modem processor data from the applicationprocessor through the interconnectivity bus after which the modemprocessor to application processor data is sent to the applicationprocessor through the interconnectivity bus.

With regards to another aspect, a method is disclosed. The methodcomprises starting an application timer at an application processor. Themethod also comprises accumulating data at the application processoruntil expiration of the application timer. The method comprises sendingthe accumulated data from the application processor to a modem processoracross an interconnectivity bus. The method further comprises holdingmodem processor data at the modem processor until receipt of theaccumulated data from the application processor.

In another aspect, a mobile terminal is disclosed. The mobile terminalcomprises a modem timer. The mobile terminal also comprises a modemprocessor. The modem processor is configured to hold modem processor toapplication processor data until expiration of the modem timer. Themobile terminal also comprises an application processor. The mobileterminal also comprises an interconnectivity bus communicativelycoupling the application processor to the modem processor. Theapplication processor is configured to hold application processor tomodem processor data until the modem processor pulls data from theapplication processor after transmission of the modem processor toapplication processor data.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1A is a simplified view of a mobile computing device operating withremote networks;

FIG. 1B is a simplified view of a mobile terminal operating with remotenetworks;

FIG. 1C is an expanded block diagram view of the mobile terminal of FIG.1B with an interconnectivity bus illustrated;

FIG. 2 is a block diagram of the mobile terminal of FIG. 1B;

FIG. 3 is an exemplary time versus link power graph in a conventionalcomputing device;

FIG. 4 is a flowchart of an exemplary process for achieving powersavings in the mobile terminal of FIG. 1B;

FIG. 5 is an exemplary time versus link power graph in a mobilecomputing device using the process of FIG. 4 ;

FIG. 6 is a flowchart of another exemplary process for achieving powersavings in the mobile computing device;

FIG. 7 is an exemplary time versus link power graph in the mobilecomputing device using the process of FIG. 6 ;

FIG. 8 is a flowchart of an exemplary process that uses a byte counterto control data accumulation;

FIG. 9 is a flowchart of an exemplary process that uses a packet counterto control data accumulation;

FIG. 10 is a flowchart of a consolidated accumulation process withoverrides illustrated from a downlink priority perspective;

FIG. 11 is a continuation of the flowchart of FIG. 10 ; and

FIG. 12 is a simplified flowchart of a consolidated accumulation processwith overrides illustrated from an uplink priority perspective.

DETAILED DESCRIPTION

With reference now to the drawing figures, several exemplary aspects ofthe present disclosure are described. The word “exemplary” is usedherein to mean “serving as an example, instance, or illustration.” Anyaspect described herein as “exemplary” is not necessarily to beconstrued as preferred or advantageous over other aspects.

Aspects disclosed in the detailed description include power savingtechniques in computing devices. In particular, as data is received by amodem processor in a computing device, the data is held until theexpiration of a modem timer. The data is then passed to an applicationprocessor in the computing device over a peripheral componentinterconnect express (PCIe) interconnectivity bus. On receipt of thedata from the modem processor, the application processor sends data heldby the application processor to the modem processor over the PCIeinterconnectivity bus. The application processor also has an uplinktimer. If no data is received from the modem processor before expirationof the uplink timer, the application processor sends any collected datato the modem processor at expiration of the uplink timer. However, ifdata is received from the modem processor, the uplink timer is reset. Byholding or accumulating the data at a source processor in this fashion,unnecessary transitions between low power states and active states onthe PCIe bus are reduced and power is conserved.

In an alternate aspect, instead of initiating data transfer based on theexpiration of the downlink timer (with or without expiration of theuplink timer), accumulated data transfer may be initiated based onexpiration of just an uplink accumulation timer. The uplink accumulationtimer may be within a host or a device associated with theinterconnectivity bus.

In another alternate aspect, initiation of the data transfer may bebased on reaching a predefined threshold for a byte accumulation limitcounter. The byte accumulation limit counter is not mutually exclusiverelative to the other counters and may operate as an override mechanismfor one of the other accumulation timers. Use of such an override may beuseful in situations where a sudden burst of data arrives that wouldexceed buffer space and/or bus bandwidth. Likewise, instead of a bytecounter, a packet size counter or a “total number of packets” countermay be used to cover situations where numerous packets or a particularlya large packet is delivered by the network.

In further aspects of the present disclosure, the timers may beoverridden by other factors or parameters. Such an override is alludedto above with the byte accumulation limit counters and the total numberof packets counter, which causes data transfers independently of thetimers. Other parameters may also override the timers, such as thepresence of low latency traffic (e.g., control messages), synchronizingthe uplink and downlink data transfers, or low latency quality ofservice requirements. When such traffic is present, an interrupt orother command may be used to initiate data transfers before expirationof a timer. Still other factors may override the timers, such as anindication that a device or host is not in an automatic polling mode.

While it is contemplated that the power saving techniques of the presentdisclosure are used in mobile terminals, such as smart phones ortablets, the present disclosure is not so limited. Accordingly, FIGS. 1Aand 1B illustrate computing devices coupled to remote networks viamodems that may implement exemplary aspects of the power savingtechniques of the present disclosure. In this regard, FIG. 1Aillustrates a computing device 10 coupled to a network 12, which, in anexemplary aspect, is the internet. The computing device 10 may include ahousing 14 with a central processing unit (CPU) (not illustrated),therein. A user may interact with the computing device 10 through a userinterface formed from input/output elements such as a monitor 16(sometimes referred to as a display), a keyboard 18, and/or a mouse 20.In some aspects, the monitor 16 may be incorporated into the housing 14.While a keyboard 18 and mouse 20 are illustrated input devices, themonitor 16 may be a touchscreen display, which may supplement or replacethe keyboard 18 and mouse 20 as an input device. Other input/outputdevices may also be present as is well understood in conjunction withdesktop or laptop style computing devices. While not illustrated in FIG.1A, the housing 14 may also include a modem, therein. The modem may bepositioned on a network interface card (NIC), as is well understood.Likewise, a router and/or an additional modem may be external to thehousing 14. For example, the computing device 10 may couple to thenetwork 12 through a router and a cable modem, as is well understood.However, even where such external routers and modems are present, thecomputing device 10 is likely to have an internal modem to effectuatecommunication with such external routers and modems.

In addition to the computing device 10, exemplary aspects of the presentdisclosure may also be implemented on a mobile terminal, which is a formof computing device as that term is used herein. In this regard, anexemplary aspect of a mobile terminal 22 is illustrated in FIG. 1B. Themobile terminal 22 may be a smart phone, such as a SAMSUNG GALAXY™ orAPPLE iPHONE®. Instead of a smart phone, the mobile terminal 22 may be acellular telephone, a tablet, a laptop, or other mobile computingdevice. The mobile terminal 22 may communicate with a remote antenna 24associated with a base station (BS) 26. The BS 26 may communicate withthe public land mobile network (PLMN) 28, the public switched telephonenetwork (PSTN, not shown), or a network 12 (e.g., the internet), similarto the network 12 in FIG. 1A. It is also possible that the PLMN 28communicates with the internet (e.g., the network 12) either directly orthrough an intervening network (e.g., the PSTN). It should beappreciated that most contemporary mobile terminals 22 allow for varioustypes of communication with elements of the network 12. For example,streaming audio, streaming video, and/or web browsing are all commonfunctions on most contemporary mobile terminals 22. Such functions areenabled through applications stored in the memory of the mobile terminal22 and using the wireless transceiver of the mobile terminal 22.

To effectuate functions, such as streaming video, data arrives from theremote antenna 24 at an antenna 30 of the mobile terminal 22, asillustrated in FIG. 1C. The data is initially processed at a mobiledevice modem (MDM) 32 of the mobile terminal 22 and passed to anapplication processor 34 by an interconnectivity bus 36. In thiscontext, the application processor 34 may be a host, and the MDM 32 maybe a device as those terms are used in the PCIe standard. Whileexemplary aspects contemplate operating over a PCIe-compliantinterconnectivity bus 36, it is possible that the interconnectivity bus36 may comply with High Speed Interconnect (HSIC), UniversalAsynchronous Receiver/Transmitter (UART), universal serial bus (USB), orthe like.

A more detailed depiction of the components of the mobile terminal 22 isprovided with reference to FIG. 2 . In this regard, a block diagram ofsome of the elements of the mobile terminal 22 of FIG. 1B isillustrated. The mobile terminal 22 may include a receiver path 38, atransmitter path 40, the antenna 30 (mentioned above with reference toFIG. 1C), a switch 42, a modem processor 44, and the applicationprocessor 34 (also introduced above in reference to FIG. 1C).Optionally, a separate control system (not shown) may also be presentwith a CPU as is well understood. The application processor 34 and themodem processor 44 are connected by the interconnectivity bus 36. Theapplication processor 34 and/or the control system (if present) mayinteroperate with a user interface 46 and memory 48 with software 50stored therein.

The receiver path 38 receives information bearing radio frequency (RF)signals from one or more remote transmitters provided by a base station(e.g., the BS 26 of FIG. 1B). A low noise amplifier (not shown)amplifies the signal. A filter (not shown) minimizes broadbandinterference in the received signal. Down conversion and digitizationcircuitry (not shown) down converts the filtered, received signal to anintermediate or baseband frequency signal. The baseband frequency signalis then digitized into one or more digital streams. The receiver path 38typically uses one or more mixing frequencies generated by the frequencysynthesizer. The modem processor 44 may include a base band processor(BBP) (not shown) that processes the digitized received signal toextract the information or data bits conveyed in the signal. As such,the BBP is typically implemented in one or more digital signalprocessors (DSPs) within the modem processor 44 or as a separateintegrated circuit (IC) as needed or desired.

With continued reference to FIG. 2 , on the transmit side, the modemprocessor 44 receives digitized data, which may represent voice, data,or control information, from the application processor 34, which itencodes for transmission. The encoded data is output to the transmitterpath 40, where it is used by a modulator (not shown) to modulate acarrier signal at a desired transmit frequency. An RF power amplifier(not shown) amplifies the modulated carrier signal to a levelappropriate for transmission, and delivers the amplified and modulatedcarrier signal to the antenna 30 through the switch 42. Collectively,the modem processor 44, the receiver path 38, and the transmitter path40 form the MDM 32 of FIG. 1C (sometimes also referred to as a wirelessmodem). While the MDM 32 is specifically described with relation to theRF signals associated with a cellular signal, the present disclosure isnot so limited. For example, a wireless modem using other wirelessprotocols may also benefit from inclusion of aspects of the presentdisclosure. Thus, modems operating according to standards such asBLUETOOTH®, the various IEEE 802.11 standards, Universal MobileTelecommunications System (UMTS), High Speed Packet Access (HSPA), LongTerm Evolution (LTE), and other wireless protocols may all use aspectsof the present disclosure.

With continued reference to FIG. 2 , a user may interact with the mobileterminal 22 via the user interface 46, such as a microphone, a speaker,a keypad, and a display. Audio information encoded in the receivedsignal is recovered by the BBP, and converted into an analog signalsuitable for driving the speaker. The keypad and display enable the userto interact with the mobile terminal 22. For example, the keypad anddisplay may enable the user to input numbers to be dialed, accessaddress book information, or the like, as well as monitor call progressinformation. The memory 48 may have the software 50 therein as notedabove, which may effectuate exemplary aspects of the present disclosure.

In conventional mobile terminals that have a PCIe interconnectivity bus(i.e., the interconnectivity bus 36), the PCIe standard allows theinterconnectivity bus 36 to be placed into a sleep mode. While placingthe interconnectivity bus 36 in a sleep mode generally saves power, suchsleep modes do have a drawback in that they consume relatively largeamounts of power as they transition out of the sleep mode. This powerconsumption is exacerbated because of the asynchronous nature of thePCIe interconnectivity bus 36. That is, first data may arrive at themodem processor 44 for transmission to the application processor 34 at atime different than when the second data is ready to pass from theapplication processor 34 to the modem processor 44. This problem is notunique to the PCIe interconnectivity bus 36.

FIG. 3 illustrates a time versus link power graph 52 that highlights howdownlink data 54 may have a different transmission time than uplink data56 within a given time slot 58. In particular, the interconnectivity bus36 (FIG. 2 ) begins in a sleep or low power mode and transitions up toan active power mode by transition 60 so that the downlink data 54 maybe transmitted to the application processor 34. However, the downlinkdata 54 may not occupy the entirety of the time slot 58, and theinterconnectivity bus 36 may return to a low power state. However,subsequently, but still within the same time slot 58, the uplink data 56from the application processor 34 is sent to the modem processor 44.Accordingly, the interconnectivity bus 36 is again transitioned from thelow power state to the active power state by a second transition 62. Inan exemplary aspect, the time slot 58 is approximately one millisecondlong. Thus, if two transitions (i.e., 60, 62) from low power to activepower occur every time slot 58, then thousands of transitions 60, 62occur every second. Thousands of transitions 60, 62 consume substantialamounts of power and reduce the battery life of the mobile terminal 22.

Exemplary aspects of the present disclosure reduce the number oftransitions (i.e., 60, 62) from low power to active power bysynchronizing packet transmission from the modem processor 44 and theapplication processor 34, which in turn allows the link to be maintainedin a low power mode more efficiently since the communication on the linkis consolidated to eliminate the second power state transition. In anexemplary aspect, the data (i.e., the modem data) from the modemprocessor 44 transmits first, and the data (i.e., the application data)from the application processor 34 is sent after arrival of the modemdata and before the interconnectivity bus 36 can return to the low powerstate. The synchronization is done through the use of timers at themodem processor 44 and the application processor 34. The timers may belonger than a time slot 58 of the interconnectivity bus 36.

In a first exemplary aspect, the timer on the application processor 34is longer than the timer on the modem processor 44. The accumulation maybe done on a per logical channel basis. The timer may be configurable bythe application processor 34 using a mechanism suitable to theinterconnectivity bus 36. For example, on a fusion device using a modemhost interface (MHI) over PCIe, the timer is maintained for everyinbound MHI channel and the time value used by the timers shall beconfigured via a MHI command message or a PCIe memory mappedinput/output (MMIO) device configuration register exposed via a baseaddress register (BAR). The BAR is a PCIe standard defined mechanism bywhich a host maps the registers of a device into its virtual addressmap. For more information about MHI, the interested reader is referredto U.S. patent application Ser. No. 14/163,846, filed Jan. 24, 2013,which is herein incorporated by reference in its entirety. In otherexemplary aspects, the timer on the modem processor 44 is longer thanthe timer on the application processor 34. In still other exemplaryaspects, counters may be used in place of timers. The counters may bebit counters, packet counters, packet size counters, or the like. Inother exemplary aspects, use of such alternate counters may be combinedwith the timers. In still other exemplary aspects, other overridecriteria may allow for data to be sent before timer or counterexpiration so as to reduce latency and/or satisfy the quality of servicerequirements. The present disclosure steps through each of these aspectsin turn, beginning with the situation where there are two timers, andthe application processor 34 has a timer that is longer than the timerof the modem processor 44.

In this regard, FIG. 4 illustrates an exemplary power saving process 70.The process 70 begins with the interconnectivity bus 36 in a low powerstate (block 72). The modem timer and the application timer are started(block 74). The timers may be software stores in the modem processor 44and the application processor 34 or may be physical elements, asdesired. Data is generated by the application processor 34 and data isreceived from the network 12 by the modem processor 44. The applicationdata is held at the application processor 34 (block 76), and the modemdata is held at the modem processor 44 (block 78) while the timers arerunning. As noted above, in an exemplary aspect, the time slot 58 of theinterconnectivity bus 36 is one millisecond. In such an aspect, themodem timer may be approximately two to six milliseconds, and theapplication timer is three to seven milliseconds, or at least longerthan the modem timer. The modem timer expires (block 80). If modem datais present, the modem data is released by the modem processor 44 throughthe interconnectivity bus 36 to the application processor 34 (block 82).

The mechanism for data transfer may be initiated and controlled by themodem processor 44 (i.e., the device). For example, on a fusion deviceusing MHI over PCIe, the modem processor 44 may poll (read) the MHIchannel Context Write Pointer to determine data buffers where downlinkpackets can be transferred. The application processor 34 updates thechannel context data structure's Context Write Pointer field to point tothe data transfer descriptors without ringing an Inbound channeldoorbell. The modem processor 44 may poll for updates on the ContextWrite Pointer field as necessitated by downlink traffic. When the modemprocessor 44 runs out of buffers, i.e., a transfer ring is empty, and nobuffers are present to transfer downlink data, the modem processor 44may generate an event (e.g., an “out-of-buffer”) notification to theapplication processor 34, followed by an interrupt. Upon receiving theevent notification from the modem processor 44, the applicationprocessor 34 shall provide data buffers by updating the channel ContextWrite Pointer and shall ring the Inbound channel doorbell.

After arrival of the modem data at the application processor 34, theapplication processor 34 releases any application data that has beenheld at the application processor 34 and resets the application timer(block 84). Note that the application timer can run on the modemprocessor 44 or the application processor 34. As an alternative, themodem processor 44 may continue to pull the uplink data 56 from theapplication processor 34 until it detects no further downlink data 54activity. That is, the modem processor 44 may intersperse pulling theuplink data 56 while receiving the downlink data 54. If, however, nomodem data is present at the modem processor 44 when the modem timerexpires, the application timer continues (i.e., another millisecond)(block 86). At the expiration of the application timer, the applicationprocessor 34 sends any held data to the modem processor 44 through theinterconnectivity bus 36 (block 88). The process then repeats bystarting over (block 90).

As noted above, the uplink timer (i.e., the application timer) is, in anexemplary aspect, designed to be longer than the downlink timer (i.e.,the modem timer) to increase the uplink/downlink synchronizationwhenever the downlink timer expires. While holding data for an extratime slot adds some latency, the brief amount added is readily absorbedby the application processor 34. Likewise, this latency is consideredacceptable for the power savings. For example, by making the period ofthe modem timer twice the period of the time slot 58, the number of lowpower to active power transitions is potentially halved. Likewise, bymaking the period of the application timer six times the period of thetime slot 58, the chance of being able to “piggyback” onto the activepower state of the interconnectivity bus 36 caused by the modem data isincreased, but still frequent enough that any uplink data 56 will stillbe sent in a timely fashion even if there is no downlink data 54 totrigger releasing the uplink data 56. Similar logic can be extended tosynchronize traffic from multiple processors over the data link. In anexemplary aspect, the other processors may each have timer values higher(i.e., longer) than that of the downlink timer, and the processors canexchange their data availability information so that traffic on oneprocessor can trigger the data transfer on other processors if there isdata available to transfer.

FIG. 5 illustrates a graph 100 where the uplink data 56 follows thedownlink data 54 during an active period 102 of the interconnectivitybus 36 (FIG. 2 ). As illustrated, there is only one transition 104 fromlow power to active power per time slot 58. Thus, by consolidating thedata into a single active period 102, the overall time that is spent inlow power may be increased, thus resulting in power savings.Additionally, power spent transitioning from a low power to active powerstate is reduced by the elimination of the second transition 62.

While it is conceivable that the uplink data 56 could be sent before thedownlink data 54 (i.e., the application timer is shorter than the modemtimer), such is generally not considered optimal because there areusually far more downlink packets than uplink packets. If this aspect isused, the application processor 34 may buffer uplink data packets intolocal memory prior to initiating transfer to the modem processor 44.These accumulated packets are controlled via an uplink accumulationtimer. If there are plural channels, then a timer may be applied to eachchannel independently. When the application processor 34 is unable touse or does not have an uplink timer, the modem processor 44 may be ableto instantiate an uplink timer, and upon expiry of the uplink timer,will poll data from the application processor 34. This exemplary aspectis explained in greater detail below with reference to FIGS. 6 and 7 .

In this regard, FIG. 6 illustrates an exemplary power saving process110. The process 110 begins with the interconnectivity bus 36 in a lowpower state (block 112). The modem timer and the application timer arestarted (block 114). The timers may be software stored in the modemprocessor 44 and the application processor 34 or may be physicalelements as desired. Data is generated by the application processor 34and data is received from the network 12 by the modem processor 44. Theapplication data is held at the application processor 34 (block 116),and the modem data is held at the modem processor 44 (block 118) whilethe timers are running. As noted above, in an exemplary aspect, the timeslot 58 of the interconnectivity bus 36 is one millisecond. In such anaspect, the application timer may be approximately two milliseconds, andthe modem timer is three milliseconds, or at least longer than theapplication timer. The application timer expires (block 120). Ifapplication data is present, the application data is released by theapplication processor 34 through the interconnectivity bus 36 to themodem processor 44 (block 122).

After arrival of the application data at the modem processor 44, themodem processor 44 releases any modem data that has been held at themodem processor 44 and resets the modem timer (block 124). Note that theapplication timer can run on the modem processor 44 or the applicationprocessor 34. Likewise, the modem timer can run on the modem processor44 or the application processor 34.

With continued reference to FIG. 6 , if no application data is presentat the application processor 34 when the application timer expires, themodem timer continues (i.e., another millisecond) (block 126). At theexpiration of the modem timer, the modem processor 44 sends any helddata to the application processor 34 through the interconnectivity bus36 (block 128). The process then repeats by starting over (block 130).

As noted above, in this exemplary aspect, the uplink timer (i.e., theapplication timer) is, in an exemplary aspect, designed to be shorterthan the downlink timer (i.e., the modem timer). While holding data foran extra time slot 58 adds some latency, the brief amount added isreadily absorbed by the application processor 34. Likewise, this latencyis considered acceptable for the power savings. For example, by makingthe period of the application timer twice the period of the time slot58, the number of low power to active power transitions is lowered.Likewise, by making the period of the modem timer six times the periodof the time slot 58, the chance of being able to “piggyback” onto theactive power state of the interconnectivity bus 36 caused by theapplication data is increased, but still frequent enough that anydownlink data 54 will still be sent in a timely fashion even if there isno uplink data 56 to trigger releasing the downlink data 54. Similarlogic can be extended to synchronize traffic from multiple processorsover the data link. In an exemplary aspect, the other processors mayeach have timer values higher (i.e., longer) than that of the uplinktimer and the processors can exchange their data availabilityinformation so that traffic on one processor can trigger the datatransfer on other processors if there is data available to transfer.

FIG. 7 illustrates a graph 140 where the uplink data 56 precedes thedownlink data 54 during an active period 142 of the interconnectivitybus 36. As illustrated, there is only one transition 144 from low powerto active power per time slot 58. Thus, by consolidating the data into asingle active period 142, the overall time that is spent in low powermay be increased, thus resulting in power savings. Additionally, powerspent transitioning from a low power to active power state is reduced bythe elimination of the second transition 62.

In an exemplary aspect, the modem processor 44 may override and choosethe minima from all configured values of each of the configurableparameters (like downlink or uplink accumulation timers, byte threshold,number of packets threshold, size of packet threshold, or the like) ordownlink accumulation expiry timer values (e.g., from among the variouschannels) as the effective downlink accumulation timer expiry value.Intelligent modem processors 44 may also dynamically override or alterthe downlink accumulation timer value depending on the downlink trafficpattern, and/or may adjust the downlink accumulation timer to achieve adesired quality of service (QoS) for data and/or to control traffic. Achange of configuration can be triggered/controlled by the applicationprocessor 44 or any other processor in the system as well, via MHIcontrol or QMI signaling (such as, for inter process signaling).

In addition to, or in place of, downlink and uplink timers, a byteaccumulation limit counter may also be used by the modem processor 44for downlink traffic and the application processor 34 for uplinktraffic. This aspect may be advantageous in situations where there is asudden burst of data pushed by the network or application. Note thatthis aspect is not mutually exclusive and may be implemented as anoverride mechanism for either downlink or uplink timers. For example, ifthe downlink accumulation timer is set relatively high to conservepower, a sudden burst of data may exceed the buffer capacity of themodem processor 44, or if allowed to accumulate in memory of the modemprocessor 44, this burst of data may exceed bus bandwidth allocations onthe application processor 34. The application processor 34 can determineand configure the maximum byte accumulation limit based on its busbandwidth budget, and/or buffer size reserved for downlink datatransfer. The modem processor 44 can also choose an internal byteaccumulation limit based on the size of downlink buffer, and/orinterconnect link data throughput. With the byte accumulation limitcounters, the modem processor 44 can initiate downlink data transfer tothe application processor 34 prior to downlink accumulation timerexpiry, if and when the buffered data size exceeds the byte accumulationlimit counter. Since both the modem processor 44 and the applicationprocessor 34 may have independent recommendations for byte accumulationlimit counter, the modem processor 44 may select the minima of these twovalues to be the effective byte accumulation limit. Similar parametersmay be maintained in the application processor 34 to trigger the uplinkdata 56 transfer immediately (i.e., overriding the uplink accumulationtimer).

Instead of, or in addition to the byte accumulation limit counter, anumber of packets limit counter may be used. In an exemplary aspect, thepacket number limit counter may be of similar design, and can beemployed to add number of packet counter limits instead of byte limitsto cover cases where a large number of packets are delivered by thenetwork or an application. Again, such a packet limit counter may alsobe present or associated with the application processor 34 or the modemprocessor 44. Note, that the accumulation timers (uplink and/ordownlink) and other configuration parameters like the number ofaccumulated packets threshold, accumulated bytes threshold, and thelike, may be a function of LTE, HSPA, GERAN, or the like.

In still another exemplary aspect, the modem processor 44 or theapplication processor 34 may disable downlink or uplink accumulation incases where there is a necessity to expedite message transfer, forexample control messages (like flow control) or high QoS data traffic orlow latency traffic, as determined by the modem processor 44 or theapplication processor 34. Latency introduced by accumulation may not betolerable for these traffic classes.

Returning to the data accumulation based on amounts of data instead of astrict process, FIGS. 8 and 9 illustrate two exemplary aspects. In thisregard, FIG. 8 illustrates a process 150 illustrating a byte counterprocess. In particular, the process 150 begins with theinterconnectivity bus 36 in a low power state (block 152). The process150 starts a modem byte counter and an application byte counter (block154). Data is held at the application processor 34 (block 156) and themodem processor 44 (block 158). A control system determines if the modembyte counter has exceeded a predefined threshold (block 160) based onthe amount of data that has been held or accumulated at the modemprocessor 44.

With continued reference to FIG. 8 , if the answer to block 160 is yes,then data is sent from the modem processor 44 to the applicationprocessor 34 (block 162). After receipt of the data from the modemprocessor 44, the application processor 34 sends data (if any) that hasaccumulated at the application processor 34 to the modem processor 44(block 164). Having cleared the accumulated data at both the modemprocessor 44 and the application processor 34, the process starts over(block 166).

With continued reference to FIG. 8 , if the answer to block 160 is no,the control system determines if the data at the application bytecounter has exceeded a predefined threshold (block 168). If the answerto block 168 is no, the process 150 returns to block 156 and datacontinues to be held until a byte counter threshold is exceeded. If,however, the answer to block 168 is yes, then the data is sent from theapplication processor 34 to the modem processor 44 (block 170). Afterreceipt of the data from the application processor 34, the modemprocessor 44 sends data (if any) to the application processor 34 (block172). Having cleared the accumulated data at both the modem processor 44and the application processor 34, the process 150 starts over (block166).

While a byte counter may be effective in managing latency, anotherexemplary aspect uses a packet counter. In this regard, FIG. 9illustrates a process 180 illustrating a byte counter process. Inparticular, the process 180 begins with the interconnectivity bus 36 ina low power state (block 182). The process 180 starts a modem packetcounter and an application packet counter (block 184). Data is held atthe application processor 34 (block 186) and the modem processor 44(block 188). A control system determines if the modem packet counter hasexceeded a predefined threshold (block 190) based on the number ofpackets held or accumulated at the modem processor 44.

With continued reference to FIG. 9 , if the answer to block 190 is yes,then data is sent from the modem processor 44 to the applicationprocessor 34 (block 192). After receipt of the packets from the modemprocessor 44, the application processor 34 sends data (if any) that hasaccumulated at the application processor 34 to the modem processor 44(block 194). Having cleared the accumulated packets at both the modemprocessor 44 and the application processor 34, the process 180 startsover (block 196).

With continued reference to FIG. 9 , if the answer to block 190 is no,the control system determines if the number of packets at theapplication packet counter has exceeded a predefined threshold (block198). If the answer to block 198 is no, the process 180 returns to block186 and data continues to be held until a packet counter threshold isexceeded. If, however, the answer to block 198 is yes, then the data issent from the application processor 34 to the modem processor 44 (block200). After receipt of the packets from the application processor 34,the modem processor 44 sends data (if any) to the application processor34 (block 202). Having cleared the accumulated packets at both the modemprocessor 44 and the application processor 34, the process 180 startsover (block 196).

A similar process may be used, where instead of determining if aparticular number of bytes or packets have been accumulated, the controlsystem evaluates a size of packets or whether the system is running lowin memory. Likewise, it should be appreciated that certain priority data(e.g., a control signal or other data requiring low latency) may beassociated with a flag or other indicator that overrides the timersand/or counters of the present disclosure.

As noted above, it should be appreciated that the aspects of the presentdisclosure are not mutually exclusive and can be combined. Thecombinations are myriad in that a timer may be used at the applicationprocessor 34 with a byte counter at the modem processor 44 (or viceversa), the modem processor 44 works with a timer and a byte counter,while the application processor 34 just has a timer, and so on. In thisregard, FIGS. 10-12 are provided that illustrate how the timers and dataaccumulation counters may inter-operate. That is, FIGS. 10 and 11illustrate how the downlink timer (whether in the modem processor 44 orthe application processor 34) is used as the basis for data transmission(e.g., as illustrated in FIGS. 4 and 5 ), may be combined with the dataaccumulation counters, and is further modified by a high priority dataoverride. FIG. 12 illustrates a simplified process in which the uplinktimer combined with the data accumulation counters is used as the basisfor data transmission (e.g., as illustrated in FIGS. 6 and 7 ), modifiedby the data overrides.

In this regard, FIGS. 10 and 11 illustrate a combined process 210 thatbegins at start (block 212). The process 210 continues with the arrivalof downlink (DL) data (e.g., a packet) (block 214). The control systemevaluates if there is any priority data, control messages, and/or otherdata that requires low latency (block 216). If the answer to block 216is no, then the control system determines if a byte threshold has beencrossed (i.e., are there more than the threshold worth of bytes in theaccumulator) (block 218). If the answer to block 218 is no, then thecontrol system determines if a number of packets threshold has beencrossed (i.e., there are more than the threshold worth of packets in theaccumulator) (block 220). If the answer to block 220 is no, then thecontrol system determines if the system is running low in memory (block222). If the answer to block 222 is no, then the control systemascertains if the downlink accumulation timer is running (block 224). Ifthe answer to block 224 is yes, then the downlink data continues toaccumulate and no data transfer is initiated over the link (block 226).

With continued reference to FIG. 10 , if, however, the answer to block224 is no, the downlink timer has expired, or if any of the overridesfrom block 216, 218, 220, or 222 has been answered affirmatively, thenthe process 210 starts transfer of the accumulated data (including thecurrent packet) over the link from the modem processor 44 (alsosometimes referred to as modem (44) in the Figures) to the applicationprocessor 34 (also sometimes referred to as AP (34) in the Figures)(block 230). The control system starts or restarts the downlinkaccumulation timer and sets the downlink accumulation timer to running(block 232). The control system determines if the modem processor 44 isin an uplink (UL) polling mode (block 234). If the answer to block 234is no, then there is no uplink transfer (block 236). If, however, themodem processor 44 is polling the uplink device, then, based on thatpolling, the control system determines if there is pending uplink datafrom the application processor 34 (block 238). If there is pending data(i.e., the answer to block 238 is yes), then the application processor34 starts data transfer to the modem processor 44 (block 240). Once thedata transfer is finished, or if there was no data at block 238, thecontrol system restarts the uplink accumulation timer (block 242) andthe process 210 returns to start 212.

With continued reference to FIG. 10 , after block 226, the controlsystem determines if the downlink timer has expired (block 244). If theanswer to block 244 is no, the control system determines if a new packethas arrived (block 246). If the answer to block 246 is no, then theprocess 210 returns to block 244. If a new packet has arrived, theprocess 210 returns to the start 212. If the answer to block 244 is yes,the downlink timer has expired, the control system knows the downlinkaccumulation timer has expired (block 248). At expiration of thedownlink timer, the control system determines if there is any pendingaccumulated downlink data (block 250). If there is data at block 250,then the data is transferred at block 230. If there is no data, then thedownlink accumulation timer is set to “not running” (block 252) and theprocess 210 goes to FIG. 11 , element C. It should be appreciated thatblocks 216, 218, 220, and 222 are optional.

With reference to FIG. 11 , the process 210 may continue from block 252.At this point, the uplink accumulation timer has expired (block 254).The uplink accumulation timer will expire if there is no downlink datasince the uplink timer was restarted. The control system determines ifthere is any pending uplink data from the application processor 34(block 256). If the answer to block 256 is yes, then the applicationprocessor 34 starts the data transfer over the link from the applicationprocessor 34 to the modem processor 44 (block 258). The control systemthen restarts the uplink accumulation timer (block 260). If, however,the answer to block 256 is no, there is no data, the control systemsends an event to the application processor 34 indicating the modemprocessor 44 is expecting a doorbell/interrupt for any pending or nextpacket submission (block 262). That is, since there has been no datafrom the application processor 34 to the modem processor 44 since theprevious poll time, then the modem processor 44 may go into an interruptmode for uplink data and the modem processor 44 would expect theapplication processor 34 to send an interrupt whenever there was datapending at the application processor 34. The control system then changesthe state internally to reflect the same (block 264).

With continued reference to FIG. 11 , the modem processor 44 receives aninterrupt or other indication from the application processor 34indicating pending data in the transfer ring (block 266). The controlsystem then restarts the uplink accumulation timer and changes the stateto indicate the uplink polling mode (block 268). All the uplink data isprocessed (block 270) and the process 210 starts over.

In another alternate aspect, there may be situations where the buffersof the application processor 34 may be full and there is no room fordata from the modem processor 44. In such an event, the applicationprocessor 34 may so inform the modem processor 44, and the modemprocessor 44 may send an event to the application processor 34 toprovide an interrupt signal to the modem processor 44 when there arefree buffers.

FIG. 12 is similar to FIGS. 10 and 11 , in that it illustrates howoverrides and data counters may be used in conjunction with anaccumulation timer, but a process 280 of FIG. 12 assumes that the uplinktimer is shorter than the downlink timer (e.g., analogous to the aspectillustrated in FIGS. 6 and 7 ). The process 280 begins at start (block282). The process 280 continues with the arrival of uplink (UL) data(e.g., a packet) (block 284). The control system evaluates if there isany priority data, control messages, and/or other data that requires lowlatency (block 286). If the answer to block 286 is no, then the controlsystem determines if a byte threshold has been crossed (i.e., are theremore than the threshold worth of bytes in the accumulator) (block 288).If the answer to block 288 is no, then the control system determines ifa number of packets threshold has been crossed (i.e., there are morethan the threshold worth of packets in the accumulator) (block 290). Ifthe answer to block 290 is no, then the control system determines if thesystem is running low in memory (block 292). If the answer to block 292is no, then the control system ascertains if the device is in an uplinkpolling mode (block 294). If the answer to block 294 is yes, the deviceis in the polling mode, then the application processor 34 updates theinternal data structure/context array with uplink data packetinformation that the device can pull and update write pointersaccordingly (block 296).

With continued reference to FIG. 12 , if, however, the answer to block294 is no, the device is not in an uplink polling mode, or if any of theoverrides from blocks 286, 288, 290, or 292 has been answeredaffirmatively, then the application processor 34 updates the internaldata structure/context array with uplink data packet information thatthe device can pull and update write pointers accordingly (block 298).The application processor 34 then rings the doorbell or otherwiseinterrupts the device to indicate the availability of uplink data (block300). The application processor 34 then sets the device state to thepolling state (not the doorbell/event/interrupt mode) (block 302), andthe process repeats.

It should be appreciated that similar processes may be performed whereboth timers are in the application processor 34 or the modem processor44 or are split between the respective processors 34, 44. Likewise, oncea timer has expired, data can be pulled or pushed across theinterconnectivity bus 36 based on polling, setting doorbell registers,or other technique.

Those of skill in the art will further appreciate that the variousillustrative logical blocks, modules, circuits, and algorithms describedin connection with the aspects disclosed herein may be implemented aselectronic hardware, instructions stored in memory or in anothercomputer-readable medium and executed by a processor or other processingdevice, or combinations of both. The devices described herein may beemployed in any circuit, hardware component, IC, or IC chip, asexamples. Memory disclosed herein may be any type and size of memory andmay be configured to store any type of information desired. To clearlyillustrate this interchangeability, various illustrative components,blocks, modules, circuits, and steps have been described above generallyin terms of their functionality. How such functionality is implementeddepends upon the particular application, design choices, and/or designconstraints imposed on the overall system. Skilled artisans mayimplement the described functionality in varying ways for eachparticular application, but such implementation decisions should not beinterpreted as causing a departure from the scope of the presentdisclosure.

The various illustrative logical blocks, modules, and circuits describedin connection with the aspects disclosed herein may be implemented orperformed with a processor, a Digital Signal Processor (DSP), anApplication Specific Integrated Circuit (ASIC), a Field ProgrammableGate Array (FPGA) or other programmable logic device, discrete gate ortransistor logic, discrete hardware components, or any combinationthereof designed to perform the functions described herein. A processormay be a microprocessor, but in the alternative, the processor may beany conventional processor, controller, microcontroller, or statemachine. A processor may also be implemented as a combination ofcomputing devices, e.g., a combination of a DSP and a microprocessor, aplurality of microprocessors, one or more microprocessors in conjunctionwith a DSP core, or any other such configuration.

The aspects disclosed herein may be embodied in hardware and ininstructions that are stored in hardware, and may reside, for example,in Random Access Memory (RAM), flash memory, Read Only Memory (ROM),Electrically Programmable ROM (EPROM), Electrically ErasableProgrammable ROM (EEPROM), registers, a hard disk, a removable disk, aCD-ROM, or any other form of computer readable medium known in the art.An exemplary storage medium is coupled to the processor such that theprocessor can read information from, and write information to, thestorage medium. In the alternative, the storage medium may be integralto the processor. The processor and the storage medium may reside in anASIC. The ASIC may reside in a remote station. In the alternative, theprocessor and the storage medium may reside as discrete components in aremote station, base station, or server.

It is also noted that the operational steps described in any of theexemplary aspects herein are described to provide examples anddiscussion. The operations described may be performed in numerousdifferent sequences other than the illustrated sequences. Furthermore,operations described in a single operational step may actually beperformed in a number of different steps. Additionally, one or moreoperational steps discussed in the exemplary aspects may be combined. Itis to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications aswill be readily apparent to one of skill in the art. Those of skill inthe art will also understand that information and signals may berepresented using any of a variety of different technologies andtechniques. For example, data, instructions, commands, information,signals, bits, symbols, and chips that may be referenced throughout theabove description may be represented by voltages, currents,electromagnetic waves, magnetic fields or particles, optical fields orparticles, or any combination thereof.

The previous description of the disclosure is provided to enable anyperson skilled in the art to make or use the disclosure. Variousmodifications to the disclosure will be readily apparent to thoseskilled in the art, and the generic principles defined herein may beapplied to other variations without departing from the spirit or scopeof the disclosure. Thus, the disclosure is not intended to be limited tothe examples and designs described herein, but is to be accorded thewidest scope consistent with the principles and novel features disclosedherein.

What is claimed is:
 1. A mobile terminal comprising: a modem timer; amodem processor, the modem processor configured to hold modem processorto application processor data until expiration of the modem timer; anapplication processor; an interconnectivity bus communicatively couplingthe application processor to the modem processor; and the applicationprocessor configured to hold application processor to modem processordata until triggered by receipt of the modem processor to applicationprocessor data from the modem processor through the interconnectivitybus after which the application processor to modem processor data issent to the modem processor through the interconnectivity bus responsiveto the receipt of the modem processor to application processor data fromthe modem processor through the interconnectivity bus.
 2. The mobileterminal of claim 1, wherein the interconnectivity bus comprises aperipheral component interconnect (PCI) compliant bus.
 3. The mobileterminal of claim 2, wherein the PCI compliant bus comprises a PCIexpress (PCIe) bus.
 4. The mobile terminal of claim 1, wherein theapplication processor includes an uplink timer and the uplink timer hasa period longer than a period of the modem timer.
 5. The mobile terminalof claim 4, wherein the application processor is configured to hold theapplication processor to modem processor data until receipt of the modemprocessor to application processor data from the modem processor orexpiration of the uplink timer having a period longer than a period ofthe modem timer, whichever occurs first.
 6. The mobile terminal of claim1, wherein the modem timer is implemented in software.
 7. The mobileterminal of claim 1, wherein the modem timer has a period ofapproximately six (6) milliseconds.
 8. The mobile terminal of claim 1,wherein the modem processor comprises the modem timer.
 9. The mobileterminal of claim 1, wherein the application processor comprises themodem timer.
 10. The mobile terminal of claim 1, further comprising anapplication timer, and wherein the modem processor is configured toinstruct the application processor to send an interrupt if no data isreceived within one time slot of the application timer.
 11. The mobileterminal of claim 1, further comprising a byte accumulation limitcounter associated with the modem processor, the modem processorconfigured to send data to the application processor if a thresholdassociated with the byte accumulation limit counter is exceeded.
 12. Themobile terminal of claim 1, further comprising a packet number limitcounter associated with the modem processor, the modem processorconfigured to send data to the application processor if a thresholdassociated with the packet number limit counter is exceeded.
 13. Themobile terminal of claim 1, wherein the modem processor is configured todetermine if held data comprises a control packet and send such controlpacket before expiration of the modem timer.
 14. The mobile terminal ofclaim 3, wherein the modem processor further comprises an applicationtimer, and the modem processor is configured to pull data from theapplication processor on receipt of the modem processor to applicationprocessor data or expiration of the application timer.
 15. The mobileterminal of claim 1, further comprising a second modem processor, thesecond modem processor configured to exchange data availabilityinformation with the modem processor such that traffic on the modemprocessor can trigger data transfer for the second modem processor. 16.A method of controlling power consumption in a computing device,comprising: holding data received by a modem processor from a remotenetwork until expiration of a downlink timer; passing the data receivedby the modem processor to an application processor over aninterconnectivity bus; and holding application data generated by anapplication associated with the application processor until receipt ofthe data from the modem processor or expiration of an uplink timer,whichever occurs first, wherein receipt of the data from the modemprocessor triggers passing the data received by the applicationprocessor to the modem processor over the interconnectivity bus beforethe interconnectivity bus transitions from an active power state to alow power state.
 17. The method of claim 16, wherein passing the datacomprises passing the data over a peripheral component interface (PCI)compliant bus.
 18. The method of claim 16, wherein a period of thedownlink timer comprises six (6) milliseconds.
 19. The method of claim16, wherein a period of the uplink timer comprises seven (7)milliseconds.
 20. The method of claim 16, further comprising providingan override capability based on one of accumulated packet size,accumulated packet count, accumulated byte count, quality of servicerequirement, and control message status.
 21. The method of claim 16,further comprising holding data at a second modem processor untiltraffic on the modem processor triggers data transfer for the secondmodem processor.
 22. A mobile terminal comprising: a modem processor; anapplication timer; an application processor, the application processorconfigured to hold application processor to modem processor data untilexpiration of the application timer; an interconnectivity buscommunicatively coupling the application processor to the modemprocessor; and the modem processor configured to hold modem processor toapplication processor data until triggered by receipt of the applicationprocessor to modem processor data from the application processor throughthe interconnectivity bus after which the modem processor to applicationprocessor data is sent to the application processor through theinterconnectivity bus responsive to the receipt of the applicationprocessor to modem processor data from the application processor throughthe interconnectivity bus.
 23. The mobile terminal of claim 22, whereinthe application processor comprises the application timer.
 24. Themobile terminal of claim 22, wherein the modem processor comprises theapplication timer.
 25. The mobile terminal of claim 22, furthercomprising a byte counter counting bytes at the modem processor.
 26. Amobile terminal comprising: a modem byte accumulation limit counter; amodem processor, the modem processor configured to hold modem processorto application processor data until a predefined threshold of bytes hasbeen reached by the modem byte accumulation limit counter; anapplication processor; an interconnectivity bus communicatively couplingthe application processor to the modem processor; and the applicationprocessor configured to hold application processor to modem processordata until triggered by receipt of the modem processor to applicationprocessor data from the modem processor through the interconnectivitybus after which the application processor to modem processor data issent to the modem processor through the interconnectivity bus responsiveto the receipt of the modem processor to application processor data fromthe modem processor through the interconnectivity bus.
 27. A mobileterminal comprising: a modem packet counter; a modem processor, themodem processor configured to hold modem processor to applicationprocessor data until a predefined threshold of packets has been reachedby the modem packet counter; an application processor; aninterconnectivity bus communicatively coupling the application processorto the modem processor; and the application processor configured to holdapplication processor to modem processor data until triggered by receiptof the modem processor to application processor data from the modemprocessor through the interconnectivity bus after which the applicationprocessor to modem processor data is sent to the modem processor throughthe interconnectivity bus responsive to the receipt of the modemprocessor to application processor data from the modem processor throughthe interconnectivity bus.
 28. A mobile terminal comprising: a modemprocessor; an application byte counter; an application processor, theapplication processor configured to hold application processor to modemprocessor data until a predefined threshold of bytes has been reached bythe application byte counter; an interconnectivity bus communicativelycoupling the application processor to the modem processor; and the modemprocessor configured to hold modem processor to application processordata until triggered by receipt of the application processor to modemprocessor data from the application processor through theinterconnectivity bus after which the modem processor to applicationprocessor data is sent to the application processor through theinterconnectivity bus responsive to the receipt of the applicationprocessor to modem processor data from the application processor throughthe interconnectivity bus.
 29. A mobile terminal comprising: a modemprocessor; an application packet counter; an application processor, theapplication processor configured to hold application processor to modemprocessor data until a predefined threshold of packets has been reachedby the application packet counter; an interconnectivity buscommunicatively coupling the application processor to the modemprocessor; and the modem processor configured to hold modem processor toapplication processor data until triggered by receipt of the applicationprocessor to modem processor data from the application processor throughthe interconnectivity bus after which the modem processor to applicationprocessor data is sent to the application processor through theinterconnectivity bus responsive to the receipt of the modem processorto application processor data from the modem processor through theinterconnectivity bus.
 30. A method comprising: starting an applicationtimer at an application processor; accumulating data at the applicationprocessor until expiration of the application timer; sending theaccumulated data from the application processor to a modem processoracross an interconnectivity bus; and holding modem processor data at themodem processor until triggered by receipt of the accumulated data fromthe application processor, wherein receipt of the accumulated data fromthe application processor triggers passing the modem processor data tothe application processor over the interconnectivity bus before theinterconnectivity bus transitions from an active power state to a lowpower state.
 31. A mobile terminal comprising: a modem timer; a modemprocessor, the modem processor configured to hold modem processor toapplication processor data until expiration of the modem timer; anapplication processor; an interconnectivity bus communicatively couplingthe application processor to the modem processor; and the applicationprocessor configured to hold application processor to modem processordata until the modem processor pulls data from the application processorafter transmission of the modem processor to application processor data,wherein the modem processor is further configured pull data from theapplication processor after transmission of the modem processor toapplication processor data and before the interconnectivity bustransitions from an active power state to a low power state.
 32. Amobile terminal comprising: a modem timer; a modem processor, the modemprocessor configured to hold modem processor-to-application processordata until expiration of the modem timer; an application timer having aperiod longer than a period of the modem timer; an applicationprocessor, the application processor configured to hold applicationprocessor-to-modem processor data until the modem processor pulls datafrom the application processor; an interconnectivity bus communicativelycoupling the application processor to the modem processor, theinterconnectivity bus having an active period and a sleep period; andthe modem processor further configured, based on the period of the modemtimer and the period of the application timer, to synchronize transferof the application processor-to-modem processor data and the modemprocessor-to-application processor data during a single active period ofthe interconnectivity bus, wherein the modem processor and theapplication processor reside in the mobile terminal.
 33. The mobileterminal of claim 32, wherein the modem processor is further configuredto instruct the application processor to send an interrupt when no datais received before expiration of the application timer.
 34. The mobileterminal of claim 32, wherein the application processor is furtherconfigured to store the pulled data via a write pointer.
 35. The mobileterminal of claim 32, wherein the modem processor is further configuredto pull the data from the application processor based on a data bufferaddress set up by the application processor.
 36. A mobile terminalcomprising: a modem timer; a modem processor, the modem processorconfigured to hold modem processor-to-application processor data untilexpiration of the modem timer; an application timer; an applicationprocessor; an interconnectivity bus communicatively coupling theapplication processor to the modem processor, the interconnectivity bushaving active mode periods and low-power mode periods; and theapplication processor configured to hold application processor-to-modemprocessor data until the modem processor pulls data from the applicationprocessor on arrival of the modem processor-to-application processordata from the modem processor through the interconnectivity bus, whereinthe application processor-to-modem processor data and the modemprocessor-to-application processor data are released during a sameactive mode period and the modem processor and the application processorreside in the mobile terminal.
 37. The mobile terminal of claim 36,wherein the modem processor is further configured to instruct theapplication processor to send an interrupt when no data is receivedbefore expiration of the application timer.
 38. The mobile terminal ofclaim 36, wherein the application processor is further configured tostore the pulled data via a write pointer.
 39. The mobile terminal ofclaim 36, wherein the modem processor is further configured to pull thedata from the application processor based on a data buffer address setup by the application processor.
 40. The mobile terminal of claim 36,wherein the application timer has a period longer than a period of themodem timer.
 41. A mobile terminal comprising: a modem processorcomprising a modem timer, the modem processor configured to hold modemprocessor to application processor data until expiration of the modemtimer; an application processor; an interconnectivity buscommunicatively coupling the application processor to the modemprocessor; and the application processor configured to hold applicationprocessor to modem processor data until triggered by receipt of themodem processor to application processor data from the modem processorthrough the interconnectivity bus after which the application processorto modem processor data is sent to the modem processor through theinterconnectivity bus responsive to the receipt of the modem processorto application processor data from the modem processor through theinterconnectivity bus, wherein the interconnectivity bus comprises aperipheral component interconnect (PCI) compliant bus, wherein the PCIcompliant bus comprises a PCI express (PCIe) bus, and wherein the modemprocessor further comprises an application timer, and the modemprocessor is configured to pull data from the application processor onthe receipt of the modem processor to application processor data orexpiration of the application timer.